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esmt f49l320ua/f49l320ba elite semiconductor memory technology inc. publication date : sep. 2008 revision: 1.1 1/55 32 mbit (4m x 8/2m x 16) 3v only cmos flash memory 1. features z single supply voltage 2.7v-3.6v z fast access time: 70/90 ns z 4,194,304x8 / 2,097,152x16 switchable by byte pin compatible with jedec standard - pin-out, packages and software commands compatible with single-power supply flash z low power consumption - 20ma typical active current - 25ua typical standby current ? z 100,000 program/erase cycles typically z 20 years data retention ? z command register architecture - byte word programming (9 s/11 s typical) - byte mode : eight 8kb, sixty three 64kb sectors. - word mode : eight 4k word, sixty-three 32 k word sectors. z auto erase (chip & sector) and auto program - any combination of sectors can be erased concurrently; chip erase also provided. - automatically program and verify data at specified address z erase suspend/erase resume - suspend or resume erasing sectors to allow the read/program in another sector z secured silicon sector - 128word sector for permanent, secure identification through an 8- word random electronic serial number - - may be programmed and locked at the factory or by the - customer - accessible through a command sequence. z ready/busy (ry/ by ) - ry/ b y output pin for detection of program or erase operation completion z end of program or erase detection - data polling - toggle bits z hardware reset - hardware pin ( eset r ) resets the internal state machine to the read mode z sector protection /unprotection - hardware protect/unprotect any combination of sectors from a program or erase operation. z low v cc write inhibit is equal to or less than 2.0v z boot sector architecture - u = upper boot block - b = bottom boot block z packages available: - 48-pin tsopi - all pb-free products are rohs-compliant z cfi (common flash interface) complaint - provides device-specific information to the system, allowing host software to easily reconfigure to different flash devices. 2. ordering information part no boot speed package comments part no boot speed package comments f49l320ua-70tg upper 70 ns tsopi pb-free F49L320UA-90TG upper 90 ns tsopi pb-free f49l320ba-70tg bottom 70 ns tsopi pb-free f49l320ba-90tg bottom 90 ns tsopi pb-free 3. general description the f49l320ua/f49l320ba is a 32 megabit, 3v only cmos flash memory device organized as 4m bytes of 8 bits or 2m words of 16bits. this device is packaged in standard 48-pin tsop. it is designed to be programmed and erased both in system and can in standard eprom programmers. with access times of 70 ns and 90 ns, the f49l320ua/f49l320ba allows the operation of high-speed microprocessors. the device has separate chip enable ce , write enable we , and output enable o e controls. esmt?s memory devices reliably store memory data even after 100,000 program and erase cycles. the f49l320ua/f49l320ba is entirely pin and command set compatible with the jedec standard for 32 megabit flash memory devices. commands are written to the f49l320ua/f49l320ba features a sector erase architecture. the device array is divided into eight 8kb, sixty-three 64kb for byte mode. the device memory array is divided into eight 4k word, sixty-three 32k word sectors for word mode. sectors can be erased individually or in groups without affecting the data in other sectors. multiple-sector erase and whole chip erase capabilities provide the flexibility to revise the data in the device. the sector protect/unprotect feature disables both program and erase operations in any combin ation of the sectors of the memory. this can be achieved in-system or via programming equipment. a low v cc detector inhibits write operations on loss of power. end of program or erase is dete cted by the ready/busy status pin, data polling of dq7, or by the toggle bit i feature on dq6. once the program or erase cycle has been successfully completed, the device internally resets to the read mode. the command register using standard microprocessor write timings.
esmt f49l320ua/f49l320ba elite semiconductor memory technology inc. publication date : sep. 2008 revision: 1.1 2/55 4. pin configurations 4.1 48-pin tsop 4.2 pin description symbol pin name functions a0~a20 address input to provide memory addresses. dq0~dq14 data input/output to output data when read and receive data when write. the outputs are in tri-state when oe or ce is high. dq15/a-1 q15 (word mode) / lsb addr (byte mode) to bi-direction date i/o when byte is high to input address when byte is low ce chip enable to activate the device when ce is low. oe output enable to gate the data output buffers. we write enable to cont rol the write operations. reset reset hardware reset pin/sector protect unprotect byte word/byte selection input to select word mode or byte mode ry/ by ready/busy to check device operation status v cc power supply to provide power gnd ground nc no connection
esmt f49l320ua/f49l320ba elite semiconductor memory technology inc. publication date : sep. 2008 revision: 1.1 3/55 5. sector structure table 1: f49l320ua sector address table sector size address range sector address sector byte mode word mode byte mode(x8) word mode(x16) a20 a19 a18 a17 a16 a15 a14 a13 a12 sa0 64kbytes 32kwords 000000-00ffff 00000-07fff 0 0 0 0 0 0 x x x sa1 64kbytes 32kwords 010000-01ffff 08000-0ffff 0 0 0 0 0 1 x x x sa2 64kbytes 32kwords 020000-02ffff 10000-17fff 0 0 0 0 1 0 x x x sa3 64kbytes 32kwords 030000-03ffff 18000-1ffff 0 0 0 0 1 1 x x x sa4 64kbytes 32kwords 040000-04ffff 20000-27fff 0 0 0 1 0 0 x x x sa5 64kbytes 32kwords 050000-05ffff 28000-2ffff 0 0 0 1 0 1 x x x sa6 64kbytes 32kwords 060000-06ffff 30000-37fff 0 0 0 1 1 0 x x x sa7 64kbytes 32kwords 070000-07ffff 38000-3ffff 0 0 0 1 1 1 x x x sa8 64kbytes 32kwords 080000-08ffff 40000-47fff 0 0 1 0 0 0 x x x sa9 64kbytes 32kwords 090000-09ffff 48000-4ffff 0 0 1 0 0 1 x x x sa10 64kbytes 32kwords 0a0000-0affff 50000-57fff 0 0 1 0 1 0 x x x sa11 64kbytes 32kwords 0b0000-0bffff 58000-5ffff 0 0 1 0 1 1 x x x sa12 64kbytes 32kwords 0c0000-0cffff 60000-67fff 0 0 1 1 0 0 x x x sa13 64kbytes 32kwords 0d0000-0dffff 68000-6ffff 0 0 1 1 0 1 x x x sa14 64kbytes 32kwords 0e0000-0effff 70000-77fff 0 0 1 1 1 0 x x x sa15 64kbytes 32kwords 0f0000-0fffff 78000-7ffff 0 0 1 1 1 1 x x x sa16 64kbytes 32kwords 100000-10ffff 80000-87fff 0 1 0 0 0 0 x x x sa17 64kbytes 32kwords 110000-11ffff 88000-8ffff 0 1 0 0 0 1 x x x sa18 64kbytes 32kwords 120000-12ffff 90000-97fff 0 1 0 0 1 0 x x x sa19 64kbytes 32kwords 130000-13ffff 98000-9ffff 0 1 0 0 1 1 x x x sa20 64kbytes 32kwords 140000-14ffff a0000-a7fff 0 1 0 1 0 0 x x x sa21 64kbytes 32kwords 150000-15ffff a8000-affff 0 1 0 1 0 1 x x x sa22 64kbytes 32kwords 160000-16ffff b0000-b7fff 0 1 0 1 1 0 x x x sa23 64kbytes 32kwords 170000-17ffff b8000-bfff 0 1 0 1 1 1 x x x sa24 64kbytes 32kwords 180000-18ffff c0000-c7fff 0 1 1 0 0 0 x x x sa25 64kbytes 32kwords 190000-19ffff c8000-cffff 0 1 1 0 0 1 x x x sa26 64kbytes 32kwords 1a0000-1affff d0000-d7fff 0 1 1 0 1 0 x x x sa27 64kbytes 32kwords 1b0000-1bffff d8000-dffff 0 1 1 0 1 1 x x x sa28 64kbytes 32kwords 1c0000-1cffff e0000-e7fff 0 1 1 1 0 0 x x x sa29 64kbytes 32kwords 1d0000-1dffff e8000-effff 0 1 1 1 0 1 x x x sa30 64kbytes 32kwords 1e0000-1effff f0000-f7fff 0 1 1 1 1 0 x x x sa31 64kbytes 32kwords 1f0000-1fffff f8000-fffff 0 1 1 1 1 1 x x x sa32 64kbytes 32kwords 200000-20ffff 100000-107fff 1 0 0 0 0 0 x x x sa33 64kbytes 32kwords 210000-21ffff 108000-10ffff 1 0 0 0 0 1 x x x sa34 64kbytes 32kwords 220000-22ffff 110000-117fff 1 0 0 0 1 0 x x x
esmt f49l320ua/f49l320ba elite semiconductor memory technology inc. publication date : sep. 2008 revision: 1.1 4/55 sa35 64kbytes 32kwords 230000-23ffff 118000-11ffff 1 0 0 0 1 1 x x x sa36 64kbytes 32kwords 240000-24ffff 120000-127fff 1 0 0 1 0 0 x x x sa37 64kbytes 32kwords 250000-25ffff 128000-12ffff 1 0 0 1 0 1 x x x sa38 64kbytes 32kwords 260000-26ffff 130000-137fff 1 0 0 1 1 0 x x x sa39 64kbytes 32kwords 270000-27ffff 138000-13ffff 1 0 0 1 1 1 x x x sa40 64kbytes 32kwords 280000-28ffff 140000-147fff 1 0 1 0 0 0 x x x sa41 64kbytes 32kwords 290000-29ffff 148000-14ffff 1 0 1 0 0 1 x x x sa42 64kbytes 32kwords 2a0000-2affff 150000-157fff 1 0 1 0 1 0 x x x sa43 64kbytes 32kwords 2b0000-2bffff 158000-15ffff 1 0 1 0 1 1 x x x sa44 64kbytes 32kwords 2c0000-2cffff 160000-167fff 1 0 1 1 0 0 x x x sa45 64kbytes 32kwords 2d0000-2dffff 168000-16ffff 1 0 1 1 0 1 x x x sa46 64kbytes 32kwords 2e0000-2effff 170000-177fff 1 0 1 1 1 0 x x x sa47 64kbytes 32kwords 2f0000-2fffff 178000-17ffff 1 0 1 1 1 1 x x x sa48 64kbytes 32kwords 300000-30ffff 180000-187fff 1 1 0 0 0 0 x x x sa49 64kbytes 32kwords 310000-31ffff 188000-18ffff 1 1 0 0 0 1 x x x sa50 64kbytes 32kwords 320000-32ffff 190000-197fff 1 1 0 0 1 0 x x x sa51 64kbytes 32kwords 330000-33ffff 198000-19ffff 1 1 0 0 1 1 x x x sa52 64kbytes 32kwords 340000-34ffff 1a0000-1a7fff 1 1 0 1 0 0 x x x sa53 64kbytes 32kwords 350000-35ffff 1a8000-1affff 1 1 0 1 0 1 x x x sa54 64kbytes 32kwords 360000-36ffff 1b0000-1b7fff 1 1 0 1 1 0 x x x sa55 64kbytes 32kwords 370000-37ffff 1b8000-1bffff 1 1 0 1 1 1 x x x sa56 64kbytes 32kwords 380000-38ffff 1c0000-1c7fff 1 1 1 0 0 0 x x x sa57 64kbytes 32kwords 390000-39ffff 1c8000-1cffff 1 1 1 0 0 1 x x x sa58 64kbytes 32kwords 3a0000-3affff 1d0000-1d7fff 1 1 1 0 1 0 x x x sa59 64kbytes 32kwords 3b0000-3bffff 1d8000-1dffff 1 1 1 0 1 1 x x x sa60 64kbytes 32kwords 3c0000-3cffff 1e0000-1e7fff 1 1 1 1 0 0 x x x sa61 64kbytes 32kwords 3d0000-3dffff 1e8000-1effff 1 1 1 1 0 1 x x x sa62 64kbytes 32kwords 3e0000-3effff 1f0000-1f7fff 1 1 1 1 1 0 x x x sa63 8kbytes 4kwords 3f0000-3f1fff 1f8000-1f8fff 1 1 1 1 1 1 0 0 0 sa64 8kbytes 4kwords 3f2000-3f3fff 1f9000-1f9fff 1 1 1 1 1 1 0 0 1 sa65 8kbytes 4kwords 3f4000-3f5fff 1fa000-1fafff 1 1 1 1 1 1 0 1 0 sa66 8kbytes 4kwords 3f6000-3f7fff 1fb000-1fbfff 1 1 1 1 1 1 0 1 1 sa67 8kbytes 4kwords 3f8000-3f9fff 1fc000-1fcfff 1 1 1 1 1 1 1 0 0 sa68 8kbytes 4kwords 3fa000-3fbfff 1fd000-1fdfff 1 1 1 1 1 1 1 0 1 sa69 8kbytes 4kwords 3fc000-3fdfff 1fe000-1fefff 1 1 1 1 1 1 1 1 0 sa70 8kbytes 4kwords 3fe000-3fffff 1ff000-1fffff 1 1 1 1 1 1 1 1 1 note: byte mode: address range a20 : a-1, word mode : address range a20 : a0
esmt f49l320ua/f49l320ba elite semiconductor memory technology inc. publication date : sep. 2008 revision: 1.1 5/55 table 2: f49l320ba sector address table sector size address range sector address sector byte mode word mode byte mode(x8) word mode(x16) a20 a19 a18 a17 a16 a15 a14 a13 a12 sa0 8kbytes 4kwords 000000-001fff 00000-00fff 0 0 0 0 0 0 0 0 0 sa1 8kbytes 4kwords 002000-003fff 01000-01fff 0 0 0 0 0 0 0 0 1 sa2 8kbytes 4kwords 004000-005fff 02000-02fff 0 0 0 0 0 0 0 1 0 sa3 8kbytes 4kwords 006000-007fff 03000-03fff 0 0 0 0 0 0 1 1 1 sa4 8kbytes 4kwords 008000-009fff 04000-04fff 0 0 0 0 0 0 1 0 0 sa5 8kbytes 4kwords 00a000-00bfff 05000-05fff 0 0 0 0 0 0 1 0 1 sa6 8kbytes 4kwords 00c000-00dfff 06000-06fff 0 0 0 0 0 0 1 1 0 sa7 8kbytes 4kwords 00e000-00ffff 07000-07fff 0 0 0 0 0 0 1 1 1 sa8 64kbytes 32kwords 010000-01ffff 08000-0ffff 0 0 0 0 0 1 x x x sa9 64kbytes 32kwords 020000-02ffff 010000-017fff 0 0 0 0 1 0 x x x sa10 64kbytes 32kwords 030000-03ffff 018000-01ffff 0 0 0 0 1 1 x x x sa11 64kbytes 32kwords 040000-04ffff 020000-027fff 0 0 0 1 0 0 x x x sa12 64kbytes 32kwords 050000-05ffff 028000-02ffff 0 0 0 1 0 1 x x x sa13 64kbytes 32kwords 060000-06ffff 030000-037fff 0 0 0 1 1 0 x x x sa14 64kbytes 32kwords 070000-07ffff 038000-03ffff 0 0 0 1 1 1 x x x sa15 64kbytes 32kwords 080000-08ffff 040000-047fff 0 0 1 0 0 0 x x x sa16 64kbytes 32kwords 090000-09ffff 048000-04ffff 0 0 1 0 0 1 x x x sa17 64kbytes 32kwords 0a0000-0affff 050000-057fff 0 0 1 0 1 0 x x x sa18 64kbytes 32kwords 0b0000-0bffff 058000-05ffff 0 0 1 0 1 1 x x x sa19 64kbytes 32kwords 0c0000-0cffff 060000-067fff 0 0 1 1 0 0 x x x sa20 64kbytes 32kwords 0d0000-0dffff 068000-06ffff 0 0 1 1 0 1 x x x sa21 64kbytes 32kwords 0e0000-0effff 070000-077fff 0 0 1 1 1 0 x x x sa22 64kbytes 32kwords 0f0000-0fffff 078000-07ffff 0 0 1 1 1 1 x x x sa23 64kbytes 32kwords 100000-10ffff 080000-087fff 0 1 0 0 0 0 x x x sa24 64kbytes 32kwords 110000-11ffff 088000-08ffff 0 1 0 0 0 1 x x x sa25 64kbytes 32kwords 120000-12ffff 090000-097fff 0 1 0 0 1 0 x x x sa26 64kbytes 32kwords 130000-13ffff 098000-09ffff 0 1 0 0 1 1 x x x sa27 64kbytes 32kwords 140000-14ffff 0a0000-0a7fff 0 1 0 1 0 0 x x x sa28 64kbytes 32kwords 150000-15ffff 0a8000-0affff 0 1 0 1 0 1 x x x sa29 64kbytes 32kwords 160000-16ffff 0b0000-0b7fff 0 1 0 1 1 0 x x x sa30 64kbytes 32kwords 170000-17ffff 0b8000-0bffff 0 1 0 1 1 1 x x x sa31 64kbytes 32kwords 180000-18ffff 0c0000-0c7fff 0 1 1 0 0 0 x x x sa32 64kbytes 32kwords 190000-19ffff 0c8000-0cffff 0 1 1 0 0 1 x x x sa33 64kbytes 32kwords 1a0000-1affff 0d0000-0d7fff 0 1 1 0 1 0 x x x sa34 64kbytes 32kwords 1b0000-1bffff 0d8000-0dffff 0 1 1 0 1 1 x x x sa35 64kbytes 32kwords 1c0000-1cffff 0e0000-0e7fff 0 1 1 1 0 0 x x x
esmt f49l320ua/f49l320ba elite semiconductor memory technology inc. publication date : sep. 2008 revision: 1.1 6/55 sa36 64kbytes 32kwords 1d0000-1dffff 0e8000-0effff 0 1 1 1 0 1 x x x sa37 64kbytes 32kwords 1e0000-1effff 0f0000-0f7fff 0 1 1 1 1 0 x x x sa38 64kbytes 32kwords 1f0000-1fffff 0f8000-0fffff 0 1 1 1 1 1 x x x sa39 64kbytes 32kwords 200000-20ffff 100000-107fff 1 0 0 0 0 0 x x x sa40 64kbytes 32kwords 210000-21ffff 108000-10ffff 1 0 0 0 0 1 x x x sa41 64kbytes 32kwords 220000-22ffff 110000-117fff 1 0 0 0 1 0 x x x sa42 64kbytes 32kwords 230000-23ffff 118000-11ffff 1 0 0 0 1 1 x x x sa43 64kbytes 32kwords 240000-24ffff 120000-127fff 1 0 0 1 0 0 x x x sa44 64kbytes 32kwords 250000-25ffff 128000-12ffff 1 0 0 1 0 1 x x x sa45 64kbytes 32kwords 260000-26ffff 130000-137fff 1 0 0 1 1 0 x x x sa46 64kbytes 32kwords 270000-27ffff 138000-13ffff 1 0 0 1 1 1 x x x sa47 64kbytes 32kwords 280000-28ffff 140000-147fff 1 0 1 0 0 0 x x x sa48 64kbytes 32kwords 290000-29ffff 148000-14ffff 1 0 1 0 0 1 x x x sa49 64kbytes 32kwords 2a0000-2affff 150000-157fff 1 0 1 0 1 0 x x x sa50 64kbytes 32kwords 2b0000-2bffff 158000-15ffff 1 0 1 0 1 1 x x x sa51 64kbytes 32kwords 2c0000-2cffff 160000-167fff 1 0 1 1 0 0 x x x sa52 64kbytes 32kwords 2d0000-2dffff 168000-16ffff 1 0 1 1 0 1 x x x sa53 64kbytes 32kwords 2e0000-2effff 170000-177fff 1 0 1 1 1 0 x x x sa54 64kbytes 32kwords 2f0000-2fffff 178000-17ffff 1 0 1 1 1 1 x x x sa55 64kbytes 32kwords 300000-30ffff 180000-187fff 1 1 0 0 0 0 x x x sa56 64kbytes 32kwords 310000-31ffff 188000-18ffff 1 1 0 0 0 1 x x x sa57 64kbytes 32kwords 320000-32ffff 190000-197fff 1 1 0 0 1 0 x x x sa58 64kbytes 32kwords 330000-33ffff 198000-19ffff 1 1 0 0 1 1 x x x sa59 64kbytes 32kwords 340000-34ffff 1a0000-1a7fff 1 1 0 1 0 0 x x x sa60 64kbytes 32kwords 350000-35ffff 1a8000-1affff 1 1 0 1 0 1 x x x sa61 64kbytes 32kwords 360000-36ffff 1b0000-1b7fff 1 1 0 1 1 0 x x x sa62 64kbytes 32kwords 370000-37ffff 1b8000-1bffff 1 1 0 1 1 1 x x x sa63 64kbytes 32kwords 380000-38ffff 1c0000-1c7fff 1 1 1 0 0 0 x x x sa64 64kbytes 32kwords 390000-39ffff 1c8000-1cffff 1 1 1 0 0 1 x x x sa65 64kbytes 32kwords 3a0000-3affff 1d0000-1d7fff 1 1 1 0 1 0 x x x sa66 64kbytes 32kwords 3b0000-3bffff 1d8000-1dffff 1 1 1 0 1 1 x x x sa67 64kbytes 32kwords 3c0000-3cffff 1e0000-1e7fff 1 1 1 1 0 0 x x x sa68 64kbytes 32kwords 3d0000-3dffff 1e8000-1effff 1 1 1 1 0 1 x x x sa69 64kbytes 32kwords 3e0000-3effff 1f0000-1f7fff 1 1 1 1 1 0 x x x sa70 64kbytes 32kwords 3f0000-3fffff 1f8000-1fffff 1 1 1 1 1 1 x x x note: byte mode: address range a20 : a-1, word mode : address range a20 : a0
esmt f49l320ua/f49l320ba elite semiconductor memory technology inc. publication date : sep. 2008 revision: 1.1 7/55 6. functional block diagram
esmt f49l320ua/f49l320ba elite semiconductor memory technology inc. publication date : sep. 2008 revision: 1.1 8/55 7. functional description 7.1 device operation this section describes the r equirements and use of the device bus operations, which are initiated through the internal command register. the register is composed of latches that store the command, address and data information needed to execute the command. the contents of the register serve as inputs to the internal state machine. the state machine outputs dictat e the function of the device. the f49l320ua /f49l320ba features various bus operations as table 3. table 3. f49l320ua/f49l320ba operation modes selection dq8-dq15 operation ce oe we reset wp /acc addresses (note 3) dq0-dq7 byte =v ih byte =v il read l l h h l/h a in d out d out write(note1) l h l h (note 4) a in (note 5) (note 5) accelerated program l h l h v hh a in (note 5) (note 5) dq8-dq14 = high-x, dq15 = a-1 standby v cc 0.3 x x v cc 0.3 h x high-z high-z high-z output disable l h h h l/h x high-z high-z high-z reset x x x l l/h x high-z high-z high-z sector protect (note 3) l h l v id l/h sa, a6 = l, a1 = h, a0 =l (note 5) x x sector unprotect (note 3) l h l v id (note 4) sa, a6 = h, a1 = h, a0 = l (note 5) x x temporary sector unprotect x x x v id (note 4) a in (note 5) (note 5) high-z notes: 1. when the acc pin is at vhh, the device enters the accelerated program mode. see 2. addresses are a20:a0 in word mode (byte# = vih), a20:a-1 in byte mode (byte# = vil). 3. the sector protect and sector unprotect functions may also be implemented via programming equipment. 4. if wp#/acc = vil, the two outermost boot sectors remain protected. if wp#/acc = vih, the two outermost boot sector protection depends on whether they were last protec ted or unprotected. if wp#/acc = vhh, all sectors are unprotected. 5. din or dout as required by command sequenc e, data polling, or sector protection algorithm. write protect(wp#) the write protect function provides a hardware method of protec ting certain boot sectors without using vid. this function is on e of two provided by wp#/acc pin. if the system asserts vil on the wp#/a cc pin, the device disables program and erase functions in the t wo outermost 8-kbyte boot sectors independently of whether those se ctors were protected or unprotected using the method. the two outermost 8-kbyte boot sectors are the two sectors containing th e lowest addresses in a bottom-boot configured device, or the t wo sectors containing the highest addresses in a top-boot configured device. if the system asserted vih on the wp#/acc pin, the device reverts to whether the two outermost 8-kbyte boot sectors were last s et to be protected or unprotected. that is, sect or protection or unprotection for these two sectors depends on whether they were last protected or unprotected using the method.
esmt f49l320ua/f49l320ba elite semiconductor memory technology inc. publication date : sep. 2008 revision: 1.1 9/55 table 4. f49l320ua/f49l32 0ba auto-select mode (high voltage method) description mode ce# oe# we# a20 to a12 a11 to a10 a9 a8 to a7 a6 a5 to a4 a3 a2 a1 a0 dq8 to dq15 dq7 to dq0 ll 8ch l h 7fh h l 7fh manufacturer id: esmt l l h x x v id xlx hh ll x 7fh word l l h 22h f6h device id: f49l320ua byte l l h x x v id xlxlllh x f6h word l l h 22h f9h device id: f49l320ba byte l l h x x v id xlxlllh x f9h x 01h (protected) sector protection verification l l h sa x v id xlxllhl x 00h (unprotected) x 8d (factory locked) sector silicon sector indicator bit (dq7) f49l320ua l l h x x v id xlxllhh x 0d (not factory locked) x 9d (factory locked) sector silicon sector indicator bit (dq7) f49l320ba l l h x x v id xlxllhh x 1d (not factory locked) notes : l = logic low = vil, h = logic high = vih, sa = sector address, x = don?t care. 1.manufacturer and device codes may also be accessed via the software command sequence in table 5.
esmt f49l320ua/f49l320ba elite semiconductor memory technology inc. publication date : sep. 2008 revision: 1.1 10/55 reset mode : hardware reset when the eset r pin is driven low for at least a period of t rp , the device immediately terminates any operation in progress, tri-states all output pins, and ignores all read/write commands for the duration of the eset r pulse. the device also resets the internal state machine to reading array data. the operation that was interrupted should be reinitiated later once the device is ready to accept another command sequence, to ensure the data integrity. the current is reduced for the duration of the eset r pulse. when eset r is held at v ss 0. 3v, the device draws cmos standby current (i cc4 ). if eset r is held at v il but not within v ss 0. 3v, the standby current will be greater. the eset r pin may be tied to system reset circuitry. a system reset would thus reset the flash memory, enabling the system to read the boot-up firm-ware from the flash memory. if eset r is asserted during a program or erase embedded algorithm operation, the ry/ by pin remains a "0" (busy) until the internal reset operation is complete, which requires a time of t ready (during embedded algorithms). the system can thus monitor ry/ by to determine whether the reset operation is complete. if eset r is asserted when a program or erase operation is not executing, i.e. the ry/ by is ?1?, the reset operation is completed within a time of t ready (not during embedded algorithms). the system can read data after t rh when the eset r pin returns to v ih . refer to the ac characteristics tables 17 for hardware reset section & figure 23 for the timing diagram. read mode to read array data from the outputs, the system must drive the ce and oe pins to v il . ce is the power control and selects the device. o e is the output control and gates array data to the output pins. we should remain at v ih . the internal state machine is set for reading array data upon device power-up, or after a hardware reset. this ensures that no spurious alteration of the memory content occurs during the power transition. no command is necessary in this mode to obtain array data. standard microprocessor?s read cycles that assert valid addresses on the device address inputs produce valid data on the device data outputs. the device remains enabled for read access until the command register contents are altered. see ?read command? section for more information. refer to the ac read operations table 14 for timing specifications and to figure 5 for the timing diagram. i cc1 in the dc characteristics table represents the active current specification for reading array data. write mode to write a command or command sequence (which includes programming data to the device and erasing sectors of memory), the system must drive we and ce to v il , and o e to v ih . the ?program command? section has details on programming data to the device using standard command sequences. an erase operation can erase one sector, multiple sectors, or the entire device. tables 1 and 2 indicate the address space that each sector occupies. a ?sector address? consists of the address bits required to uniquely select a sector. the ?software command definitions? section has details on erasing a sector or t he entire chip, or suspending/resuming the erase operation. when the system writes the auto-select command sequence, the device enters the auto-select mode. the system can then read auto-select codes from the internal register (which is separate from the memory array) on dq7?dq0. standard read cycle timings apply in this mode. refer to the auto-select mode and auto-select command sections for more information. i cc2 in the dc characteristics table represents the active current specification for the write mode. the ?ac characteristics? section contains timing specification tables and timing diagrams for write operations. automatic sleep mode the automatic sleep mode minimizes flash device energy consumption. the device automatically enables this mode when addresses remain unchanged for over 250ns. the automatic sleep mode is independent of the ce , we , and o e control signals. standard address access timings provide new data when addresses are changed. while in sleep mode, output data is latched and always available to the system. i cc4 in the dc characteristics table represents the automatic sleep mode current specification. word / byte mode this pin controls the i/o configuration of device. when byte = v ih or vcc 0. 3v. the i/o configuration is x16 and t he pin of d15/a-1 is bi-direction data i/o. however, byte = v il or v ss 0.3v. the i/o configuration would be x8 and the pin of dq15/a-1 only address input pin. you must define the function of this pin before enable this device.
esmt f49l320ua/f49l320ba elite semiconductor memory technology inc. publication date : sep. 2008 revision: 1.1 11/55 temporary sector unprotect mode this feature allows temporary unprotection of previously protected sector to change data in-system. this mode is activated by setting the eset r pin to v id (10v-10.5v). during this mode, all formerly protected sectors are un-protected and can be programmed or erased by selecting the sector addresses. once v id is removed from the eset r pin, all the previously protected sectors are protected again. notes: 1. all protected sectors unprotected. 2. all previously protected se ctors are protected once again. start reset = v id (note 1) perform erase or program operation reset = v ih temporary sector unprotect completed (note 2) operation completed
esmt f49l320ua/f49l320ba elite semiconductor memory technology inc. publication date : sep. 2008 revision: 1.1 12/55 output disable mode with the o e is at a logic high level (v ih ), outputs from the devices are disabled. this will cause the output pins in a high impedance state standby mode when ce and eset r are both held at v cc 0.3v, the device enter cmos standby mode. if ce and eset r are held at v ih , but not within the range of v cc 03v, t he device will still be in the standby mode, but the standby current will be larger. if the device is deselected during auto algorithm of erasure or programming, the device draws active current i cc2 until the operation is completed. i cc3 in the dc characteristics table represents the standby current specification. the device requires standard access time (t ce ) for read access from either of these standby modes, before it is ready to read data. sector protect / un-protect mode the hardware sector protect feature disables both program and erase operations in any sector. the hardware sector unprotect feature re-enables both the program and erase operations in previously protected sectors. sector protect/unprotect can be implemented via two methods. the primary method requires v id on the eset r pin only, and can be implemented either in-system or via programming equipment. figure 16 shows the algorithms and figure 15 shows the timing diagram. this method uses standard microprocessor bus cycle timing. for sector unprotect, all unprotected sectors must first be protected prior to the first sector unprotect write cycle. the alternate method intended only for programming equipment requires v id on address pin a9, o e , and eset r . auto-select mode the auto-select mode provides manufacturer and device identification and sector pr otection verification, through outputs on dq7?dq0. this mode is primarily intended for programming equipment to automatically match a device to be programmed with its corresponding programming algorithm. however, the auto-select codes can also be accessed in-system through the command register. when using programming equipment, this mode requires v id (10 v to 10.5 v) on address pin a9. while address pins a3, a2, a1, and a0 must be as shown in table 4. to verify sector protection, all necessary pins have to be set as required in table 4, the programming equipment may then read the corresponding identifier code on dq7-dq0. to access the auto-select codes in-system, the host system can issue the auto-select command via the command register, as shown in table 5. this method does not require v id . see ?software command definitions? for details on using the auto-select mode. 7.2 software command definitions writing specific address and data commands or sequences into the command register initiates the device operations. table 5 defines the valid register command sequences. writing incorrect address and data values or writing them in the improper sequence resets the device to reading array data. all addresses are latched on the falling edge of we or ce , whichever happens later. all data is latched on the rising edge of we or ce , whichever happens first. refer to the corresponding timing diagrams in the ac characteristics section.
esmt f49l320ua/f49l320ba elite semiconductor memory technology inc. publication date : sep. 2008 revision: 1.1 13/55 table 5. f49l320ua/f49l320ba software command definitions bus cycle note 1~4 1st 2nd 3rd 4th 5th 6th command sequence cycles addr data addr data addr data addr data addr data addr data read note 5 1 ra rd reset note 6 1 xxx f0 x00 xx8c x04 xx7f x08 xx7f word 555 2aa 555 x0c xx7f x00 8c x04 7f x08 7f manufacturer id byte 4 aaa aa 555 55 aaa 90 x0c 7f word 555 2aa 555 x01 22f6 device id, f49l320ua byte 4 aaa aa 555 55 aaa 90 x02 f6 word 555 2aa 555 x01 22f9 device id, f49l320ba byte 4 aaa aa 555 55 aaa 90 x02 f9 word 555 2aa 555 x03 secured silicon sector factory protect f49l320ua note 8 byte 4 aaa aa 555 55 aaa 90 x06 8d/0d word 555 2aa 555 x03 secured silicon sector factory protect f49l320ba note 8 byte 4 aaa aa 555 55 aaa 90 x06 9d/1d xx00 word 555 2aa 555 (sa) x02 xx01 00 autoselect note 7 sector protect verify note 9 byte 4 aaa aa 555 55 aaa 90 (sa) x04 01 word 555 2aa 555 enter secured silicon sector region byte 3 aaa aa 555 55 aaa 88 word 555 2aa 555 exit secured silicon sector region byte 4 aaa aa 555 55 aaa 90 xxx 00 word 55 cfi query note 10 byte 1 aa 98 word 555 2aa 555 program byte 4 aaa aa 555 55 aaa a0 pa pd word 555 2aa 555 555 2aa 555 chip erase byte 6 aaa aa 555 55 aaa 80 aaa aa 555 55 aaa 10 word 555 2aa 555 555 2aa sector erase byte 6 aaa aa 555 55 aaa 80 aaa aa 555 55 sa 30 erase suspend note 11 1 xxx b0 erase resume note 12 1 xxx 30
esmt f49l320ua/f49l320ba elite semiconductor memory technology inc. publication date : sep. 2008 revision: 1.1 14/55 legend: x = don?t care ra = address of the memory location to be read. rd = data read from location ra during read operation. pa = address of the memory location to be programmed. addresses latch on the falling edge of the we# or ce# pulse, whichever happens later. pd = data to be programmed at location pa. data latches on the rising edge of we# or ce# pulse, whichever happens first. sa = address of the sector to be verified (in autoselect mode) or erased. address bits a20?a12 uniquely select any sector. notes: 1.all values are in hexadecimal. 2.except for the read cycle and the fourth cycle of the aut oselect command sequence, all bus cycles are write cycles. 3.data bits dq15?dq8 are don?t cares for unlock and command cycles. 4.address bits a20?a11 are don?t cares for unlock and command cycles, unless sa or pa required. 5.no unlock or command cycles required when reading array data. 6. the reset command is required to return to reading array data when device is in the autoselect mode, or if dq5 goes high (while the device is providing status data). 7.the fourth cycle of the autoselect command sequence is a read cycle. 8. for word mode data is 8dh for factory locked and 0dh for not factory locked. for byte mode data is 9dh for factory locked an d 1dh for not factory locked. 9.the data is 00h for an unprotected sector and 01h for a protected sector. see ? autoselect command sequence? for more information. 10.command is valid when device is ready to read array data or when device is in autoselect mode. 11.the system may read and program in non-erasing sectors, or enter the autoselect mode, when in the erase suspend mode. the erase suspend command is valid onl y during a sector erase operation. 12.the erase resume command is valid only during the erase suspend mode.
esmt f49l320ua/f49l320ba elite semiconductor memory technology inc. publication date : sep. 2008 revision: 1.1 15/55 reset command writing the reset command to the device resets the device to reading array data. address bits are all don?t cares for this command. the reset command may be written between the sequence cycles in an erase command sequence before erasing begins. this resets the device to reading array data. once erasure begins, however, the device ignores reset commands until the operation is complete. the reset command may be written between the sequence cycles in a program command sequence before programming begins. this resets the device to reading array data (also applies to programming in erase suspend mode). once programming begins, however, the device ignores reset commands until the operation is complete. the reset command may be written between the sequence cycles in an auto-select command sequence. once in the auto-select mode, the reset command must be written to return to reading array data (also applies to auto-select during erase suspend). if dq5 goes high (see ?dq5: exceeded timing limits? section) during a program or erase operation, writing the reset command returns the device to reading array data (also applies during erase suspend). read command the device is automatically set to reading array data after device power-up. no commands are required to retrieve data. the device is also ready to read array data after completing an embedded program or embedded erase algorithm. when the device accepts an erase suspend command, the device enters the erase suspend mode. the system can read array data using the standard read timings, except that if it reads an address within erase-suspended sectors, the device outputs status data. after completing a programming operation in the erase suspend mode, the system may once again read array data with the same exception. see ?erase suspend/erase resume commands? for more information on this mode. the system must issue the reset command to re-enable the device for reading array data if dq5 goes high, or while in the auto-select mode. see the ?reset command? section. see also the ?read mode? in the ?device operations section for more information. refer to figure 5 for the timing diagram. program command the program command sequence programs one byte into the device. programming is a four-bus-cycle operation. the program command sequence is initiated by writing two unlock write cycles, followed by the program set-up command. the program address and data are written next, which in turn initiate the embedded program algorithm. the system is not required to provide further controls or timings. the device automatically provides internally generated program pulses and verifies the programmed cell margin. when the embedded program algorithm is complete, the device then returns to reading array data and addresses are no longer latched. the system can determine the status of the program operation by using dq7, dq6, or ry/ by . see ?write operation status? section for more information on these status bits. any commands written to the device during the embedded program algorithm are ignored. note that a hardware reset immediately terminates the programming operation. the program command sequence should be reinitiated once the device has reset to reading array data, to ensure data integrity. programming is allowed in any sequence and across sector boundaries. a bit cannot be programmed from a ?0? back to a ?1?. attempting to do so may halt the operation and set dq5 to ?1?, or cause the data polling algorithm to indicate the operation was successful. however, a succeeding read will show that the data is still ?0?. only erase operations can convert a ?0? to a ?1?. chip erase command chip erase is a six-bus cycle operation. the chip erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. two additional unlock write cycles are then followed by the chip erase command, which in turn invokes the embedded erase algorithm. the device does not require the system to preprogram prior to erase. the embedded erase algorithm automatically preprograms and verifies the entire memory for an all zero data pattern prior to electrical erase. any commands written to the chip during the embedded erase algorithm are ignored. note that a hardware reset during the chip erase operation immediately terminates the operation. the chip erase command sequence should be reinitiated once the device has returned to reading array data, to ensure the data integrity.
esmt f49l320ua/f49l320ba elite semiconductor memory technology inc. publication date : sep. 2008 revision: 1.1 16/55 the system can determine the status of the erase operation by using dq7, dq6, dq2, or ry/ by . see ?write operation status? section for more information on these status bits. when the embedded erase algorithm is complete, the device returns to reading array data and addresses are no longer latched. see the eras e/program operations tables in ?ac characteristics? for parameters. sector erase command sector erase is a six-bus cycle operation. the sector erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. two additional unlock write cycles are then followed by the address of the sector to be erased, and the sector erase command. the device does not require the system to preprogram the memory prior to erase. the embedded erase algorithm automatically programs and verifies the sector for an all zero data pattern prior to electrical erase. the system is not required to provide any controls or timings during these operations. after the command sequence is written, a sector erase time-out of 50 s begins. driving the time-out period, additional sector addresses and sector erase commands may be written. loading the sector erase buffer may be done in any sequence, and the number of sectors may be from one sector to all sectors. the time between these additional cycles must be less than 50 s, otherwise the last address and command might not be accepted, and erasure may begin. it is recommended that processor interrupts be disabled during this time to ensure all commands are accepted. the interrupts can be re-enabled after the last sector erase command is written. if the time between additional sector erase commands can be assumed to be less than 50 s, the system need not monitor dq3. any command other than sector erase or erase suspend during the time-out period resets the device to reading array data. the system must rewrite the command sequence and any additional sector addresses and commands. the system can monitor dq3 to determine if the sector erase timer has timed out. (see the ?dq3: sector erase timer? section.) the time-out begins from the rising edge of the final we pulse in the command sequence. once the sector erase operation has begun, only the erase suspend command is valid. all other commands are ignored. note that a hardware reset during the sector erase operation immediately terminates the operation. the sector erase command sequence should be reinitiated once the device has returned to reading array data, to ensure the data integrity. when the embedded erase algorithm is complete, the device returns to reading array data and addresses are no longer latched. the system can determine the status of the erase operation by using dq7, dq6, dq2, or ry/ by . (refer to ?write operation status? section for more information on these status bits.) refer to the erase/program operations tables in the ?ac characteristics? section for parameters. sector erase suspend/resume command the erase suspend command allows the system to interrupt a sector erase operation and then read data from, or program data to, any sector not selected for erasure (the device ? erase suspends? all sect or selected for erasure.). this command is valid only during the sector erase operation, including the 50 s time-out period during the sector erase command sequence. the erase suspend command is ignored if written during the chip erase operation or embedded program algorithm. addresses are ?don?t -cares? when writing the erase suspend command as shown in table 5. when the erase suspend command is written during a sector erase operation, the device requires a maximum of 20s to suspend the erase operation. however, when the erase suspend command is written during the sector erase time-out, the device immediately terminates the time-out period and suspends the erase operation. reading at any address within erase-suspended sectors produces status data on dq7?dq0. the system can use dq7, or dq6 and dq2 together, to determine if a sector is actively erasing or is erase-suspended. see ?write operation status? section for more information on these status bits. after an erase-suspended program operation is complete, the system can once again read array data within non-suspended sectors. the system can determine the status of the program oper ation using the dq7 or dq6
esmt f49l320ua/f49l320ba elite semiconductor memory technology inc. publication date : sep. 2008 revision: 1.1 17/55 status bits, just as in the standard program operation. see ?write operation status? f or more information. the system may also write the auto-select command sequence when the device is in the erase suspend mode. the device allows reading auto-select codes even at addresses within erasing sectors, since the codes are not stored in the memory array. when the device exits the auto-select mode, the device reverts to the erase suspend mode, and is ready for another valid operation. after an erase-suspended program operation is complete, the system can once again read array data within non-suspended sectors. the system can determine the status of the program operat ion using the dq7 or dq6 status bits, just as in the standard program operation. see ?write operation status? f or more information. the system may also write the auto-select command sequence when the device is in the erase suspend mode. the device allows reading auto-select codes even at addresses within erasing sectors, since the codes are not stored in the memory array. when the device exits the auto-select mode, the device reverts to the erase suspend mode, and is ready for another valid operation. the system must write the erase resume command (address bits are ?don?t care? as shown in table 5) to exit the erase suspend mode and continue the sector erase operation. further writes of the resume command are ignored. another erase suspend command can be written after the device has resumed erasing. auto-select command the auto-select command sequence allows the host system to access the manufacturer and devices codes, and determine whether or not a sector is protected. table 6 shows the address and data requirements. this method is an alternative to that shown in table 4, which is intended for prom programmers and requires v id on address bit a9. the auto-select command sequence is initiated by writing two unlock cycles, followed by the auto-select command. the device then enters the auto-select mode, and the system may read at any address any number of times, without initiating another command sequence. the read cycles at address 04h, 08h, 0ch, and 00h retrieves the esmt manufacturer id. a read cycle at address 01h retrieves the device id. a read cycle containing a sector address(sa) and the address 02h returns 01h if that sector is protected, or 00h if it is unprotected. refer to tables 1 and 2 for valid sector addresses. the system must write the reset command to exit the auto-select mode and return to reading array data. 7.3 write operation status the device provides several bits to determine the status of a write operation: ry/ by , dq7, dq6, dq5, dq3, dq2, and. table 7 and the following subsections describe the functions of these bits. ry/ by , dq7, and dq6 each offer a method for determining whether a program or erase operation is complete or in progress. table 7. write operation status status dq7 (note1) dq6 dq5 (note2) dq3 dq2 ry/ by embedded program algorithm 7 dq toggle 0 n/a no toggle 0 embedded erase algorithm 0 toggle 0 1 toggle 0 reading erase suspended sector 1 no toggle 0 n/a toggle 1 reading non-erase suspended sector data data data data data 1 in progress erase suspended mode erase suspend program 7 dq toggle 0 n/a n/a 0 embedded program algorithm 7 dq toggle 1 n/a no toggle 0 embedded erase algorithm 0 toggle 1 1 toggle 0 exceeded time limits erase suspend program 7 dq toggle 1 n/a n/a 0 notes: 1. dq7 and dq2 require a valid address when reading status inform ation. refer to the appropriate subsection for further details . 2. dq5 switches to ?1? when an embedded program or embedd ed erase operation has exceeded the maximum timing limits. see ?dq5: exceeded timing limits? for more information.
esmt f49l320ua/f49l320ba elite semiconductor memory technology inc. publication date : sep. 2008 revision: 1.1 18/55 ry/ by : ready/busy the ry/ by is a dedicated, open-drain output pin that indicates whether an embedded algorithm is in progress or complete. the ry/ by status is valid after the rising edge of the final we pulse in the command sequence. since ry/ by is an open-drain output, several ry/ by pins can be tied together in parallel with a pull-up resistor to v cc . if the output is low (busy), the device is actively erasing or programming. (this includes programming in the erase suspend mode.) if the output is high (ready), the device is ready to read array data (including during the erase suspend mode), or is in the standby mode. table 7 shows the outputs for ry/ by . dq7: data polling the dq7 indicates to the host system whether an embedded algorithm is in progress or completed, or whether the device is in erase suspend mode. the data polling is valid after the rising edge of the final we pulse in the program or erase command sequence. during the embedded program algorithm, the device outputs on dq7 the complement of the datum programmed to dq7. this dq7 status also applies to programming during erase suspend. when the embedded program algorithm is complete, the device outputs the true data on dq7. the system must provide the program address to read valid status information on dq7. if a program address falls within a protected sector, data polling on dq7 is active for approximately 1 s, then the device returns to reading array data. during the embedded erase algorithm, data polling produces a ?0? on dq7. when the embedded erase algorithm is complete, or if the device enters the erase suspend mode, data polling produces a ?1? on dq7. the system must provide an address within any of the sectors selected for erasure to read valid status information on dq7. after an erase command sequence is written, if all sectors selected for erasing are protected, data polling on dq7 is active for approximately 100 s, then the device returns to reading array data. if not all selected sectors are protected, the embedded erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. when the system detects dq7 has changed from the complement to true data, it can read valid data at dq7~ dq0 on the following read cycles. this is because dq7 may change asynchronously with dq0?dq6 while output enable ( o e ) is asserted low. refer to figure 21, data polling timings (during embedded algorithms), figure 19 shows the data polling algorithm. dq6:toggle bit i toggle bit i on dq6 indicates whether an embedded program or erase algorithm is in progress or complete, or whether the device has entered the erase suspend mode. toggle bit i may be read at any address, and is valid after the rising edge of the final we pulse in the command sequence (prior to the program or erase operation), and during the sector erase time-out. during an embedded program or erase algorithm operation, successive read cycles to any address cause dq6 to toggle. the system may use either o e or ce to control the read cycles. when the operation is complete, dq6 stops toggling. when an erase command sequence is written, if all sectors selected for erasing are protected, dq6 toggles for approximately 100 s, then returns to reading array data. if not all selected sectors are protected, the embedded erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. the system can use dq6 and dq2 together to determine whether a sector is actively erasing or is erase-suspended. when the device is actively erasing (i.e. the embedded erase algorithm is in progress), dq6 toggles. when the dev ice enters the erase suspend mode, dq6 stops toggling. however, the system must also use dq2 to determine which sectors are erasing or erase-suspe nded. alternatively, the system can use dq7. if a program address falls within a protected sector, dq6 toggles for approximately 2s after the program command sequence is written, then returns to reading array data. dq6 also toggles during the erase-suspend-program mode, and stops toggling once the embedded program algorithm is complete. table 7 shows the outputs for toggle bit i on dq6. figure 20 shows the toggle bit algorithm. figure 22 shows the toggle bit timing diagrams. figure 25 shows the differences between dq2 and dq6 in graphical form. refer to the subsection on dq2: toggle bit ii. dq2: toggle bit ii the ?toggle bit ii? on dq2, when used with dq6, indicates whether a particular sector is actively erasing (that is, the embedded erase al gorithm is in progress), or whether that sector is erase-suspended. toggle bit ii is valid after the rising edge of the final or ce , whichever happens first, in the command sequence.
esmt f49l320ua/f49l320ba elite semiconductor memory technology inc. publication date : sep. 2008 revision: 1.1 19/55 dq2 toggles when the system reads at addresses within those sectors that have been selected for erasure. (the system may use either o e or ce to control the read cycles.) but dq2 cannot distinguish whether the sector is actively erasing or is erase-suspended. dq6, by comparison, indicates whether the device is actively erasing, or whether is in erase-suspended, but cannot distinguish which sectors are selected for erasure. thus, both status bits are required for sector and mode information. refer to table 7 to compare outputs for dq2 and dq6. figure 20 shows the toggle bit algorithm in flowchart form. see also the dq6: toggle bit i subsection. figure 22 shows the toggle bit timing diagram. figure 25 shows the differences between dq2 and dq6 in graphical form. reading toggle bits dq6/ dq2 refer to figure 20 for the following discussion. whenever the system initially begins reading toggle bit status, it must read dq7?dq0 at least twice in a row to determine whether a toggle bit is toggling. typically, the system would note and store the value of the toggle bit after the first read. after the second read, the system would compare the new value of the toggle bit with the first. if the toggle bit is not toggling, the device has completed the program or erase operation. the system can read array data on dq7?dq0 on the following read cycle. however, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the system should note whether the value of dq5 is high (see the section on dq5). if it is, the system should then determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as dq5 went high. if the toggle bit is no longer toggling, the device has successfully completed the program or erase operation. if it is still toggling, the device did not completed the operation successfully, and the system must write the reset command to return to reading array data. the remaining scenario is that the system initially determines that the toggle bit is toggling and dq5 has not gone high. the system may continue to monitor the toggle bit and dq5 through successive read cycles, determining the status as described earlier. alternatively, it may choose to perform other system tasks. in this case, the system must start at the beginning of the algorithm when it returns to determine the status of the operation. dq5: exceeded timing limits dq5 indicates whether the program or erase time has exceeded the specified limits(internal pulse count). under these conditions dq5 will produce a "1". this time-out condition indicates that the program or erase cycle was not successfully completed. data polling and toggle bit are the only operating functions of the device under this condition. if this time-out condition occurs during sector erase operation, it specifies that a particular sector is bad and it may not be reused. however, other sectors are still functional and may be used for the program or erase operation. the device must be reset to use other sectors. write the reset command sequence to the device, and then execute program or erase command sequence. this allows the system to continue to use the other active sectors in the device. if this time-out condition occurs during the chip erase operation, it specifies that the entire chip is bad or combination of sectors are bad. if this time-out condition occurs during the programming operation, it specifies that the sector containing that byte is bad and this sector may not be reused, however other sectors are still functional and can be reused. the time-out condition will not appear if a user tries to program a non blank location without erasing. please note that this is not a device failure condition since the device was incorrectly used. dq3:sector erase timer after writing a sector erase command sequence, the system may read dq3 to determine whether or not an erase operation has begun. (the sector erase timer does not apply to the chip erase command.) if additional sectors are selected for erasure, the entire timeout also applies after each additional sector erase command. when the time-out is complete, dq3 switches from ? 0? to ? 1.? if the time between additional sector erase commands from the system can be assumed to be less than 50 s, the system need not monitor dq3. when the sector erase command sequence is written, the system should read the status on dq7 (data polling) or dq6 (toggle bit i) to ensure the device has accepted the command sequence, and then read dq3. if dq3 is ? 1?, the internally controlled erase cycle has begun; all further commands (except erase suspend) are ignored until the erase operation is complete. if dq3 is ? 0?, the device will accept additional sector erase commands. to ensure the command has been accepted, the system software should check the status of dq3 prior to and following each subsequent sector erase command. if dq3 is high on the second status check, the last command might not have been accepted. table 7 shows the outputs for dq3.
esmt f49l320ua/f49l320ba elite semiconductor memory technology inc. publication date : sep. 2008 revision: 1.1 20/55 customer lockable : secured silicon sector not programmed or protected at the factory the customer lockable version allows the secured silicon sector to be programmed once, and then permanently locked after it ships. note that the accelerated programming (acc) is not available when programming the secured silicon sector. the secured silicon sector area can be protected using the following procedures: ? write the three-cycl e enter secured silicon region command sequence, and then follow the in-system sector protect algorithm as shown in figure 16. of page41, except that reset# may be eit her vih or vid. this allows in system protection of the secured silicon sector without raising any device pin to a high voltage. note that this method is only applicable to the secured silicon sector. ? to verify the protect/unprotect status of the secured silicon sector, follow the algorithm shown in below table. once the secured silicon sector protection must be used with caution since, once protected, there is no procedure available for unprotecting the secured silicon sector area, and none of the bits in the secured silicon sector memory space can be modified in any way. factory locked : secured silicon sector programmed and protected at the factory the secured silic on sector feat ure provides a 256 ?byte flash memory region that enables permanent part identific ation through an electronic serial number (esn). the secured silicon sector uses a secured silicon sector indicator bit (dq7) to indicate whether or not the secured silicon sector is locked when shipped from the factory. factory locked version the bit( dq7) set to 1, customer lockable version the bit (dq7) set to 0. in a factory locked device, the secured silicon sector cannot be modified in any way. the device is available pre-programmed with one of the following: 1. a random, secure esn only. 2. customer code through the express flash service. 3. both a random, secure esn and customer code through the express flash device. in device that have an esn, a bottom boot device has the 16-byte (8-word) esn in sector 0 at address 00000h-0000fh in byte mode(or 00000h~00007h in word mode).in the top boot device, the ecn is in sector 70 at addresses 3fff00h-3fff0fh in byte mode ( or 1fff80h-1fff87h in word mode). in the uniform device, the esn is in sector 63 at addresses 3fff00h-3fff0fh in byte mode (or 1fff80h- 1fff87h in word mode). customers may opt to have their code programmed by esmt through the express-flash service. esmt programs the customer?s code, with or without the random esn. the devices are then shipped from the esmt factory with the secured silicon sector locked. note: 1. after entering secured silicon sector mode, user can program secured s ilicon sector (means to write esn code) and do secured silicon sector protection once when device is customer lockable version. 2. enter secured silicon sector mode, the under functions are not allowed except for cfi. a. sector erase/erase suspend/resume. b. chip erase. 3. secured silicon sector mode doesn?t have ?erase? and ?unprotect? function.
esmt f49l320ua/f49l320ba elite semiconductor memory technology inc. publication date : sep. 2008 revision: 1.1 21/55 word mode secured silicon sector addresses sector address a20~12 sector size ( bytes/words) ( x8 ) address range ( x16 ) address range 111111111 256/128 3fff00h-3fffffh 1fff80h-1fffffh byte mode secured s ilicon sector addresses sector address a20~12 sector size ( bytes/words) ( x8 ) address range ( x16 ) address range 000000000 256/128 000000h-0000ffh 000000h-00007fh 7.4 more device operations hardware data protection the command sequence requirement of unlock cycles for programming or erasing provides data protection against inadvertent writes. in addition, the following hardware data protection measures prevent accidental erasure or programming, which might otherwise be caused by spurious system level signals during v cc power-up and power-down transitions, or from system noise. low v cc write inhibit when v cc is less than v lko , the device does not accept any write cycles. this protects data during v cc power-up and power-down. the command register and all internal program/erase circuits are disabled, and the device resets. subsequent writes are ignored until v cc is greater than v lko . the system must provide the proper signals to the control pins to prevent unintentional writes when v cc is greater than v lko . write pulse "glitch" protection noise pulses of less than 5 ns (typical) on ce or we do not initiate a write cycle. logical inhibit write cycles are inhibited by holding any one of o e = v il , ce = v ih or we = v ih . to initiate a write cycle, ce and we must be a logical zero while o e is a logical one. power supply decoupling in order to reduce power switching effect, each device should have a 0.1uf cera mic capacitor connected between its v cc and gnd. power-up sequence the device powers up in the read mode. in addition, the memory contents may only be altered after successful completion of the predefined command sequences. power-up write inhibit if we = ce = v il and o e = v ih during power up, the device does not accept commands on the rising edge of we . the internal state machine is automatically reset to reading array data on power-up.
esmt f49l320ua/f49l320ba elite semiconductor memory technology inc. publication date : sep. 2008 revision: 1.1 22/55 common flash memory interface (cfi) the common flash interface (cfi) specification outlines device and host system software interrogation handshake, which allows specific vendor-specified software algorithms to be used for entire families of devices. softwa re support can then be device-in dependent, jedec id-independent, and forward- and backward- compatible for the specified flash device families. flash vendors can standard ize their existing interfaces for long-term compatibility. this device enters the cfi query mode when the system writes the cfi query command, 98h, to address 55h in word mode (or addres s aah in byte mode), any time the device is ready to array data. the system can read cfi information at the address given in tabl es 8-10 in word mode, the upper address bits (a7-msb) must be all zeros. to terminate reading cfi data, the system must write the reset command. the system can also write the cfi query command when the device is in the autoselect mode. the device enters the cfi query mode , and the system can read cfi data at the addresses given in tables 8-10. the system must write the reset command to return the d evice to the autoselect mode. table 8 cfi query identification string addresses (word mode) address (byte mode) data description 10h 11h 12h 20h 22h 24h 0051h 0052h 0059h query unique ascii string ?qry? 13h 14h 26h 28h 0002h 0000h primary oem command set 15h 16h 2ah 2ch 0040h 0000h address for primary extended table 17h 18h 2eh 30h 0000h 0000h alternate oem command set (00h = none exists) 19h 1ah 32h 34h 0000h 0000h address for alternate oem extended table (00h = none exists)
esmt f49l320ua/f49l320ba elite semiconductor memory technology inc. publication date : sep. 2008 revision: 1.1 23/55 table 9 system interface string addresses (word mode) address (byte mode) data description 1bh 36h 0027h v cc min. (write/erase) d7~d4 : volt, d3~d0 : 100 millivolt 1ch 38h 0036h v cc max. (write/erase) d7~d4 : volt, d3~d0 : 100 millivolt 1dh 3ah 0000h v pp min. voltage (00h = no v pp pin present) 1eh 3ch 0000h v pp max. voltage (00h = no v pp pin present) 1fh 3eh 0004h typical timeout per single byte/word write 2 n s 20h 40h 0000h typical timeout for min. size buffer write 2 n s (00h = not supported) 21h 42h 000ah typical timeout per individual block erase 2 n ms 22h 44h 0000h typical timeout for full chip erase 2 n ms (00h = not supported) 23h 46h 0005h max. timeout for byte/word write 2 n word times typical 24h 48h 0000h max. timeout for buffer write 2 n word times typical 25h 4ah 0004h max. timeout per individual block erase 2 n word times typical 26h 4ch 0000h max. timeout per full chip erase 2 n word times typical (00h = not supported) table 10 device geometry definition addresses (word mode) address (byte mode) data description 27h 4eh 0016h device size = 2 n byte 28h 29h 50h 52h 0002h 0000h flash device interface description (refer to cfi publication 100) 2ah 2bh 54h 56h 0000h 0000h max. number of byte in multi-byte write = 2 n (00h = not supported) 2ch 58h 0002h number of erase block regions within device 2dh 2eh 2fh 30h 5ah 5ch 5eh 60h 0007h 0000h 0020h 0000h erase block region 1 information (refer to the cfi specification or cfi publication 100) 31h 32h 33h 34h 62h 64h 66h 68h 003eh 0000h 0000h 0001h erase block region 2 information 35h 36h 37h 38h 6ah 6ch 6eh 70h 0000h 0000h 0000h 0000h erase block region 3 information 39h 3ah 3bh 3ch 72h 74h 76h 78h 0000h 0000h 0000h 0000h erase block region 4 information
esmt f49l320ua/f49l320ba elite semiconductor memory technology inc. publication date : sep. 2008 revision: 1.1 24/55 table 11 primary vendor-specific extended query addresses (word mode) address (byte mode) data description 40h 41h 42h 80h 82h 84h 0050h 0052h 0049h query-unique ascii string ? pri? 43h 86h 0031h major version number, ascii 44h 88h 0031h minor version number, ascii 45h 8ah 0000h address sensitive unlock 0 = required, 1 = not required 46h 8ch 0002h erase suspend 0 = not supported, 1 = to read only, 2 = to read & write 47h 8eh 0001h erase protect 0 = not supported, x = number of sectors in per group 48h 90h 0001h sector temporary unprotect 00 = not supported, 01 = supported 49h 92h 0004h sector protect/group unprotect scheme 4ah 94h 0000h simultaneous operation 00 = not supported, 01 = supported 4bh 96h 0000h burst mode type 00 = not supported, 01 = supported 4ch 98h 0000h page mode type 00 = not supported, 01 = 4 word page, 02 = 8 word page 4dh 9ah 00b5h acc (acceleration) supply minimum 00h = not supported, d7-d4 : volt, d3-d0 : 100mv 4eh 9ch 00c5h acc (acceleration) supply maximum 00h = not supported, d7-d4 : volt, d3-d0 : 100mv 4fh 9eh 000xh top / bottom boot sector flag (02h = bottom boot device, 03h = top boot device)
esmt f49l320ua/f49l320ba elite semiconductor memory technology inc. publication date : sep. 2008 revision: 1.1 25/55 8. absolute maximum ratings storage temperature plastic packages . . . . . . . . . . . . . . ?65 c to +150 c ambient temperature with power applied. . . . . . . .. . . . . . ?65 c to +125 c voltage with respect to ground v cc (note 1) . . . . . . . . . . .?0.5 v to +4.0 v a9 , o e , and eset r (note 2) . . . ?0.5 v to +10.5v all other pins (note 1). . . . . . . . . . ?0.5 v to v cc +0.5 v output short circuit current (note 3) .. . .. 200 ma notes: 1. minimum dc voltage on input or i/o pins is ?0.5 v. during voltage transitions, input or i/o pins may overshoot v ss to ?2.0 v for periods of up to 20 ns. see figure 1. maximum dc voltage on input or i/o pins is v cc +0.5 v. during voltage transitions, input or i/o pins may overshoot to v cc +2.0 v for periods up to 20 ns. see figure 2. 2. minimum dc input voltage on pins a9, o e , and eset r is -0.5 v. during voltage transitions, a9, o e , and eset r may overshoot v ss to ?2.0 v for periods of up to 20 ns. see figure 1. maximum dc input voltage on pin a9 is +10.5v which may overshoot to 14v periods up to 20 ns. 3. no more than one output may be shorted to ground at a time. duration of the short circuit should not be greater than one second. stresses above those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this data sheet is not implied. exposure of the device to absolute maximum rating conditions for extended periods may affect device reliability. figure 1. maximum negative overshoot waveform figure 2. maximum positive overshoot waveform +0.8v -0.5v -2.0v 20ns 20ns 20ns vcc +2.0v vcc +0.5v 2.0v 20ns 20ns 20ns
esmt f49l320ua/f49l320ba elite semiconductor memory technology inc. publication date : sep. 2008 revision: 1.1 26/55 operating ranges commercial (c) devices ambient temperature (ta) . . . . . . . . . . . 0 c to +70c v cc supply voltages v cc for all devices . . . . . . . . . . . . . . . . . . . . .2.7 v to 3.6 v operating ranges define those limits between which the functionality of the device is guaranteed. table 12. capacitance t a = 25c , f = 1.0 mhz symbol description conditions min. typ. max. unit c in1 input capacitance v in = 0v 8 pf c in2 control pin capacitance v in = 0v 12 pf c out output capacitance v out = 0v 12 pf 9. dc characteristics table 13. dc characteristics t a = 0 c to 70 c, v cc = 2.7v to 3.6v symbol description conditions min. typ. max. unit i li input leakage current v in = v ss or v cc , v cc = v cc max. 1 ua i lit a9 input leakage current v cc = v cc max; a9=10.5v 35 ua i lo output leakage current v out = v ss or v cc , v cc = v cc max 1 ua @5mhz 9 25 ma ce = v il , o e = v ih ( byte mode ) @1mhz 2 5 ma @5mhz 9 40 ma i cc1 v cc active read current ce = v il , o e = v ih ( word mode ) @1mhz 2 5 ma i cc2 v cc active write current ce = v il , o e = v ih 20 50 ma i cc3 v cc standby current ce ; eset r = v cc 0.3v 25 100 ua i cc4 v cc standby current during reset eset r = v ss 0.3v 25 100 ua i cc5 automatic sleep mode v ih = v cc 0.3v; v il = v ss 0.3v 25 100 ua v il input low voltage(note 1) -0.5 0.8 v v ih input high voltage 0.7x v cc v cc + 0.3 v v id voltage for auto-select and temporary sector unprotect v cc =3.3v 10 10.5 v v ol output low voltage i ol = 4.0ma, v cc = v cc min 0.45 v v oh1 output high voltage(ttl) i oh = -2ma, v cc = v cc min 0.7x v cc v oh2 output high voltage i oh = -100ua, v cc min v cc -0.4 v lko low v cc lock-out voltage 2.3 2.5 v notes : 1. v il min. = -1.0v for pulse width is equal to or less than 50 ns. v il min. = -2.0v for pulse width is equal to or less than 20 ns. 2. v ih max. = v cc + 1.5v for pulse width is equal to or less than 20 ns if v ih is over the specified maximum value, read operation cannot be guaranteed. 3. automatic sleep mode enable the low power mode when addresses remain stable for t acc + 30 ns
esmt f49l320ua/f49l320ba elite semiconductor memory technology inc. publication date : sep. 2008 revision: 1.1 27/55 10. ac characteristics test conditions figure 3. test setup figure 4. input waveforms and measurement levels input 3.0v 0v 1.5v output 1.5v test points ac testing : inputs are driven at 3.0v for a logic "1" and 0v for a logic "0" input pulse rise and fall times are < 5ns.
esmt f49l320ua/f49l320ba elite semiconductor memory technology inc. publication date : sep. 2008 revision: 1.1 28/55 10.1 read operation ta = 0 c to 70 c, v cc = 2.7v~3.6v table 14. read operations -70 -90 symbol description conditions min. max. min. max. unit t rc read cycle time (note 1) 70 90 ns t acc address to output delay ce = o e = v il 70 90 ns t ce ce to output delay o e = v il 70 90 ns t oe o e to output delay ce = v il 30 35 ns t df o e high to output float (note1) ce = v il 25 30 ns output enable read 0 0 ns t oeh hold time toggle and data polling 10 10 ns t oh address to output hold ce = oe = v il 0 0 ns notes : 1. not 100% tested. 2. t df is defined as the time at which the output achieves the open circuit condition and data is no longer driven. figure 5. read timing waveform t rc addresses stable output valid address high-z ce we 0v ry/by reset oe outputs high-z t acc t oeh t oe t oh t df t ce
esmt f49l320ua/f49l320ba elite semiconductor memory technology inc. publication date : sep. 2008 revision: 1.1 29/55 10.2 program/erase operation table 15. we controlled program/erase operations(t a = 0 c to 70 c, v cc = 2.7v~3.6v) -70 -90 symbol description min. max. min. max. unit t wc write cycle time (note 1) 70 90 ns t as address setup time 0 0 ns t ah address hold time 45 45 ns t ds data setup time 35 45 ns t dh data hold time 0 0 ns t oes output enable setup time 0 0 ns t ghwl read recovery time before write ( o e high to we l ow) 0 0 ns t cs ce setup time 0 0 ns t ch ce hold time 0 0 ns t wp write pulse width 35 35 ns t wph write pulse width high 30 30 ns byte 9(typ.) 9(typ.) t whwh1 programming operation (note 2) word 11(typ.) 11(typ.) us t whwh2 sector erase operation (note 2) 0.7(typ.) 0.7(typ.) sec t vcs v cc setup time (note 1) 50 50 us t rb recovery time from ry/ by 0 0 ns t busy program/erase valid to ry/ by delay 90 90 ns notes : 1. not 100% tested. 2. see the "erase and programming performance" section for more information.
esmt f49l320ua/f49l320ba elite semiconductor memory technology inc. publication date : sep. 2008 revision: 1.1 30/55 table 16. ce controlled program/erase operations(t a = 0 c to 70 c, v cc = 2.7v~3.6v) -70 -90 symbol description min. max. min. max. unit t wc write cycle time (note 1) 70 90 ns t as address setup time 0 0 ns t ah address hold time 45 45 ns t ds data setup time 35 45 ns t dh data hold time 0 0 ns t oes output enable setup time 0 0 ns t ghel read recovery time before write 0 0 ns t ws we setup time 0 0 ns t wh we hold time 0 0 ns t cp ce pulse width 35 35 ns t cph ce pulse width high 30 30 ns byte 9(typ.) 9(typ.) us t whwh1 programming operation(note2) word 11(typ.) 11(typ.) us t whwh2 sector erase operation (not e2) 0.7(typ.) 0.7(typ.) sec notes : 1. not 100% tested. 2. see the "erase and programming performance" section for more information.
esmt f49l320ua/f49l320ba elite semiconductor memory technology inc. publication date : sep. 2008 revision: 1.1 31/55 figure 6. write command timing waveform oe data v ih v il add valid v ih v il v ih v il v ih v il v ih v il t ah t as t wp t wph vcc 3v address we ce t cwc t cs t ch t dh t ds din t oes
esmt f49l320ua/f49l320ba elite semiconductor memory technology inc. publication date : sep. 2008 revision: 1.1 32/55 figure 7. embedded programming timing waveform notes : 1. pa = program address, pd = program data , dout is the true data the program address. ce we address oe 555h pa pa pa t wc t as read status data (last two cycle) t ah t ch t ghwl t wp t cs t wph a0h t ds t dh pd status dout t whwh1 data t vcs vcc program command sequence (last two cycle) ry/by t rb t busy
esmt f49l320ua/f49l320ba elite semiconductor memory technology inc. publication date : sep. 2008 revision: 1.1 33/55 figure 8. embedded programming algorithm flowchart start write data aah address 555h verify work ok? embedded program completed data poll from system yes last address? yes no write data 55h address 2aah write data a0h address 555h no increment address write program data/address
esmt f49l320ua/f49l320ba elite semiconductor memory technology inc. publication date : sep. 2008 revision: 1.1 34/55 figure 9. ce controlled program timing waveform notes : 1. pa = program address, pd = program data, dout = data out , dq7 = complement of data written to device 2. figure indicates the last two bus cycles of the command sequence.. address we ce oe 555 for program 2aa for erase data polling t as t wc pa data reset ry/by pa for program sa for sector erase 555 for chip erase a0 for program 55 for erase pd for program 30 for sector erase 10 for chip erase t wh t ah t ds t dh t ghel t cp t cph t busy t ws dout dq7 t whwh1 or 2 t rh
esmt f49l320ua/f49l320ba elite semiconductor memory technology inc. publication date : sep. 2008 revision: 1.1 35/55 figure 10. embedded chip erase timing waveform notes : sa = sector address (for sector erase, va = valid address for reading status data (see "write operation status") address ce we oe 2aah 555h va va t wc t as erase command sequence(last two cycle) read status data t ah t ch t ghwl t wp t cs t wph 55h t ds t dh 10h in progress complete t whwh2 data t rb t busy ry/by t vcs vcc
esmt f49l320ua/f49l320ba elite semiconductor memory technology inc. publication date : sep. 2008 revision: 1.1 36/55 figure 11. embedded chip erase algorithm flowchart start write data aah address 555h embedded chip erease completed data = ffh? yes no write data 55h address 2aah write data 80h address 555h write data aah address 555h write data 55h address 2aah write data 10h address 555h data poll from system
esmt f49l320ua/f49l320ba elite semiconductor memory technology inc. publication date : sep. 2008 revision: 1.1 37/55 figure 12. embedded sector erase timing waveform notes : sa = sector address (for sector erase, va = valid address for reading status data (see "write operation status") address ce we oe 2aah sa va va t wc t as erase command sequence(last two cycle) read status data t ah t ch t ghwl t wp t cs t wph 55h t ds t dh 30h in progress complete t whwh2 data t rb t busy ry/by t vcs vcc
esmt f49l320ua/f49l320ba elite semiconductor memory technology inc. publication date : sep. 2008 revision: 1.1 38/55 figure 13. embedded sector erase algorithm flowchart start write data aah address 555h embedded sector erease completed last sector to erase yes no write data 55h address 2aah write data 80h address 555h write data aah address 555h write data 55h address 2aah write data 30h address sa data poll from system data = ffh? no
esmt f49l320ua/f49l320ba elite semiconductor memory technology inc. publication date : sep. 2008 revision: 1.1 39/55 figure 14. erase suspend/erase resume flowchart start write data b0h toggle bit checking q6 not toggled yes erase resume no erase suspend read array or program another erase suspend? no no yes reading or programming end yes write data 30h continue erase
esmt f49l320ua/f49l320ba elite semiconductor memory technology inc. publication date : sep. 2008 revision: 1.1 40/55 figure 15. in-system sector protect/unprotect timing waveform ( rese t control) notes : when sector protect, a6=0, a1=1, a0=0. when sector unprotect, a6=1, a1=1, a0=0. ce reset sa,a6 a1,a0 data 1us sector protect sector unprotect valid* valid* valid* 60h 60h 40h status verify we sector protect = 150us sector unprotect = 15ms oe v id v ih
esmt f49l320ua/f49l320ba elite semiconductor memory technology inc. publication date : sep. 2008 revision: 1.1 41/55 figure 16. in-system sector protect/unprotect algorithm ( rese t = v id ) start start plscnt = 1 plscnt = 1 set up first sector address sector unprotect : write 60h to sector address with a6 = 1, a1 = 1, a0 = 0 wait 15 ms? first write cycle = 60h? all sectors protected? data = 00h? last sector verified? no reset = v id no no yes yes no no no yes yes first write cycle = 60h? temporary sector unprotect mode set up next sector address device failed device failed yes wait 1 s? temporary sector unprotect mode data = 01h? yes reset = v id plscnt = 1000? wait 1 s? increment plscnt set up sector address sector protect : write 60h to sector address with a6 = 0, a1 = 1, a0 = 0 verify sector protect : write 40h to sector address with a6 = 0, a1 = 1, a0 = 0 wait 150 s? read from sector address with a6 = 0, a1 = 1, a0 = 0 plscnt = 25? increment plscnt protect another sector? no no no remove v id from reset remove v id from reset write reset command write reset command sector protect complete sector protect complete sector protect algorithm sector unprotect algorithm yes reset plscnt = 1 protect all sector : the indicated portion of the sector protect algorithm must be performed for all unprotected sectors prior to issuing the first sector unprotect address yes yes read from sector address with a6 = 1, a1 = 1, a0 =0 verify sector unprotect : write 40h to sector address with a6 = 1, a1 = 1, a0 =0
esmt f49l320ua/f49l320ba elite semiconductor memory technology inc. publication date : sep. 2008 revision: 1.1 42/55 figure 17. sector protect timing waveform (a9, oe control)
esmt f49l320ua/f49l320ba elite semiconductor memory technology inc. publication date : sep. 2008 revision: 1.1 43/55 figure 18. sector protection algorithm (a9, oe control) start set up sector address data = 01h? sector protection complete activate we pluse remove vid from a9 write reset command device failed protect another sector? yes yes no no plscnt = 1 oe = v id , a9 = v id , ce = v il a6 = v il time out 150us set we = v ih , ce = oe = v il a9 should remain v id read from sector address = sa, a0=1, a1 = 1 plscnt = 32?
esmt f49l320ua/f49l320ba elite semiconductor memory technology inc. publication date : sep. 2008 revision: 1.1 44/55 write operation status figure 19. data polling algorithm notes : 1. va =valid address for programming. 2. dq7 should be re-checked even dq5 = "1" because dq7 may change simultaneously with dq5. start read dq7~dq0 add. = va(1) dq7 = data? fail pass dq5 = 1? no read dq7~dq0 add. = va yes yes no dq7 = data? yes no (2)
esmt f49l320ua/f49l320ba elite semiconductor memory technology inc. publication date : sep. 2008 revision: 1.1 45/55 figure 20. toggle bit algorithm note : 1. read toggle bit twice to determine whether or not it is toggle. 2. recheck toggle bit because it may stop toggling as dq5 change to "1". start read dq7 ~ dq0 toggle bit = dq6 toggle? program / erase operation not complete, write reset command program / erase operation complete dq5 = 1? no read dq7~dq0 twice yes no toggle bit dq6 = toggle? no yes yes read dq7 ~ dq0 (note 1) (note 1,2)
esmt f49l320ua/f49l320ba elite semiconductor memory technology inc. publication date : sep. 2008 revision: 1.1 46/55 figure 21. data polling timings (during embedded algorithms) notes : va = valid address. figure shows first status cycle after command sequence, last status read cycle, and array data read cycle. we address ce oe t acc dq7 ry/by t ce va va t rc t oe t oeh t ch t df t oh complement complement true vaild data high-z status data status data true vaild data high-z dq0~dq6 t busy
esmt f49l320ua/f49l320ba elite semiconductor memory technology inc. publication date : sep. 2008 revision: 1.1 47/55 figure 22. toggle bit timing wavefo rms (during embedded algorithms) notes : va = valid address; not required for dq6. figure shows first status cycle after command sequence, last status read cycle, and array data read cycle. address ce oe we t acc dq6/dq2 ry/by t ce va va t rc t oe t oeh t ch t df t oh vaild status t busy va vaild status va high-z (fi rst read) (second read) vaild data (stops toggling) vaild data
esmt f49l320ua/f49l320ba elite semiconductor memory technology inc. publication date : sep. 2008 revision: 1.1 48/55 10.3 hardware reset operation table 17. ac characteristics symbol description all speed options unit t ready1 eset r pin low (during embedded algorithms) to read or write (see note) max 20 us t ready2 eset r pin low (not during embedded algorithms) to read or write (see note) max 500 ns t rp eset r pulse width (during embedded algorithms) min 500 ns t rh eset r high time before read(see note) min 50 ns t rb ry/ by recovery time(to ce , o e go low) min 0 ns notes : not 100% tested figure 23. rese t timing waveform ry/by ce, oe reset ry/by ce, oe reset t rp t ready2 t rh t rp t rb t ready1 reset timing not during automatic algorithms reset timing during automatic algorithms
esmt f49l320ua/f49l320ba elite semiconductor memory technology inc. publication date : sep. 2008 revision: 1.1 49/55 10.4 temporary sector unprotect operation table 18. temporary sector unprotect symbol description all speed options unit t vidr v id rise and fall time (see note) min 500 ns t rsp eset r setup time for temporary sector unprotect min 4 us notes: not 100% tested figure 24. temporary sector unprotect timing diagram figure 25. dq6 vs dq2 for erase and erase suspend operations notes : the system can use oe or ce to toggle dq2 / dq6, dq2 toggle s only when read at an address within an erase-suspended. we dq6 dq2 enter embedded erasing erase suspend enter erase suspend program erase suspend program erase suspend read erase resume erase erase complete we ry/by ce reset t vidr t rsp 0 or v cc program or erase command sequence t vidr 0 or v cc 12v 10
esmt f49l320ua/f49l320ba elite semiconductor memory technology inc. publication date : sep. 2008 revision: 1.1 50/55 figure 26. temporary sector unprotect algorithm notes : 1. all protected status are temporary unprotect. v id = 10v~10.5v 2. all previously protected sectors are protected again. start reset = v id (note 1) reset = v ih program erase or program operation temporary sector unprotect completed (note 2) operation completed
esmt f49l320ua/f49l320ba elite semiconductor memory technology inc. publication date : sep. 2008 revision: 1.1 51/55 figure 27. id code read timing waveform
esmt f49l320ua/f49l320ba elite semiconductor memory technology inc. publication date : sep. 2008 revision: 1.1 52/55 11. erase and programming performance table 19. erase and programming performance (note.1) limits parameter typ.(2) max.(3) unit sector erase time 0.7 15 sec chip erase time 25 50 sec byte programming time 9 300 us word programming time 11 360 us byte mode 36 108 sec chip programming time word mode 24 72 sec erase/program cycles (1) 100,000 cycles data retention 20 years notes: 1.not 100% tested, excludes external system level over head. 2.typical values measured at 25 c, 3.3v. 3.maximum values measured at 85 c, 2.7v.
esmt f49l320ua/f49l320ba elite semiconductor memory technology inc. publication date : sep. 2008 revision: 1.1 53/55 12. package dimension 48-lead tsop(i) ( 12x20 mm ) dimension in mm dimension in inch dimension in mm dimension in inch symbol min norm max min norm max symbol min norm max min norm max a ------- ---- --- 1.20 ------- -- ----- 0.047 d 20.00 bsc 0.787 bsc a 1 0.05 ------- 0.15 0.006 ------- 0.002 d 1 18.40 bsc 0.724 bsc a 2 0.95 1.00 1.05 0.037 0.039 0. 041 e 12.00 bsc 0.472 bsc b 0.17 0.22 0.27 0.007 0.009 0.011 e 0.50 bsc 0.020 bsc b1 0.17 0.20 0.23 0.007 0.008 0.009 l 0.50 0.60 0.70 0.020 0.024 0.028 c 0.10 ------- 0.21 0.004 ------- 0.008 0 o ------- 8 o 0 o ------- 8 o c1 0.10 ------- 0. 16 0.004 ------- 0.006
esmt f49l320ua/f49l320ba elite semiconductor memory technology inc. publication date : sep. 2008 revision: 1.1 54/55 revision history revision date description 0.1 2007.05.31 original 0.2 2007.10.01 modify manufacturer id command 0.3 2007.11.28 add unlock bypass program description 0.4 2008.01.14 1.remove unlock bypass program description 2.add ?all pb-free products are rohs ? compliant? to features 3.modify icc spec and v ih , v ioh1 1.0 2008.08.20 1. delete preliminary 2. add revision history 3. add cfi address (4dh-4fh) 1.1 2008.09.30 modify chip erase time
esmt f49l320ua/f49l320ba elite semiconductor memory technology inc. publication date : sep. 2008 revision: 1.1 55/55 important notice all rights reserved. no part of this document may be reproduced or duplicated in any form or by any means without the prior permission of esmt. the contents contained in this docum ent are believed to be accurate at the time of publication. esmt assu mes no responsibilit y for any error in this document, and reserves the right to change the products or specification in this document without notice. the information contained herein is presented only as a guide or examples for the application of o ur products. no responsibility is assumed by esmt for any infringement of patents, copyrights, or other intellectual property rights of third part ies which may result from its use. no license, either express , implied or otherwise, is granted under any patents, copyrights or other inte llectual property rights of esmt or others. any semiconductor devices may have i nherently a certain rate of failure. to minimize risks associated with customer's application, adequate design and operating safeguards agains t injury, damage, or loss from such failure, should be provided by the customer when making application designs. esmt's products are not authorized for us e in critical applications such as, but not limited to, life support devices or system, where failure or abnormal operation may directly affect human lives or cause physical injury or property damage. if products described here are to be used for such kinds of applicatio n, purchaser must do its own quality assurance testing appropriate to such applications.

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